The present invention relates to bipolar semiconductor devices, in particular bipolar transistors and semiconductor diodes, which are electrically isolated or confined by trenches.
When manufacturing bipolar transistors one can use a highly doped inner layer, a bottom diffusion or xe2x80x9cburied layerxe2x80x9d. The purpose of this bottom diffusion layer is to reduce the collector series resistance for NPN-transistors and to serve as a base connection for corresponding lateral PNP-transistors. By introducing a highly doped bottom diffusion, in the cases usually of type N+, the performance of the components can be considerably improved. Such a bottom diffusion, which is produced before an epitaxial layer is grown on the silicon plate, on which the components are built, is then connected from the component surface through a region comprising a deep diffusion of type N+. In this region a doping has first been made at the surface and then the atoms introduced in the doping process have been made to diffuse deeply down into the silicon plate by a suitable heat treatment. The individual components manufactured on the same silicon plate can be isolated from each other by areas comprising deep P-diffiusions, which extend through the epitaxial layer down to the inner or interior material of the silicon plate, i.e., the substrate, which in these cases is silicon of P-type.
For the NPN-transistor shown in FIG. 1, the highly doped inner layer or bottom diffusion layer 1 is produced by diffusion from the surface of the P-substrate 3, before the epitaxial layer 5 of N-type is grown on the silicon plate 3. The bottom diffusion 1 is located under the whole active area 7 of the collector and is intended to reduce the series resistance of the collector connection. This series resistance is for NPN-transistors normally determined by a rather thin region of the weakly doped silicon layer of N-type, which forms the active collector area 7. By shunting in this way the weakly doped, very collector layer 7 by a highly doped bottom diffusion 1 which has a lower resistivity and is type N+ for NPN-transistors, component performance can be considerably improved, i.e., the resistance between the exterior collector contact 9 and the active portion 7 of the collector is reduced. The bottom diffusion 1 of type N+ is then connected from the surface of the component through a deep localized diffusion 11 of type N+ for obtaining a so called collector plug, the upper surface of which is connected to the exterior collector contact 9. The bottom diffusion layer 1 is furthermore located so that it extends under all of the active area of the transistor. It thus extends under all of the very base in the P-layer 13 and under the emitter layer 15, which is doped to N+. The individual transistors are isolated from each other by deep localized diffusion regions 17 of type P+, which extend through the epitaxial layer 5 down to the substrate 3, which, as has already been indicated, in the standard case is P-type silicon.
In some IC-applications also lateral bipolar transistors of PNP-type are also used, see FIGS. 2a and 2b. In this case the bottom diffusion layer 21, which also in this case is of type N+, constitutes a connection to the very base 23, which is an epitaxial N-layer. In order to further reduce the contact resistance to the base 23 here a deep localized diffusion 25 of type N+ is also used, which extends from the surface of the component down to the bottom diffusion 21. The bottom diffusion 21 also in this case extends under all of the active area of the transistor, i.e., under the very collector 27 of type P+ and all of the emitter 29, which is also doped to P+. The bottom diffusion 21 is as above produced by diffusion from the surface of the P-substrate 31. In the plan view of FIG. 2b the generally square layout of the PNP-transistor appears, the various regions or areas forming square structures or square frame-like or annular structures.
The advantages of using a bottom diffusion in this case comprise:
i) that the base resistance is reduced
ii) that the concentration of holes in the connection intermediate region or junction between the epitaxial layer 23 which is of N-type and the substrate 31 of P-type is reduced. Thereby, the current gain is reduced for the vertical-parasitic PNP-transistor, which is formed by substrate-base-emitter or substrate-base-collector.
In that way a better current amplification and a better frequency behavior are obtained in the PNP-transistor.
Also in this case the components can be isolated from each other by deep P-diffusions, not shown, which extend through the epitaxial layer 23 down to the substrate 31, which is P-type silicon.
When manufacturing high frequency transistors, for which one wants to obtain very high performance, it is common to replace the isolating, deep localized diffusions 17 of type P+, as mentioned above in conjunction with FIG. 1 and intended for isolating individual components such as transistors, by ditches etched deeply down into the silicon having at least in their upper portions substantially vertical side walls, so called xe2x80x9ctrenchesxe2x80x9d, see FIG. 7 and e.g. P. C. Hunt and M. P. Cooke, xe2x80x9cProcess HE: A highly advanced trench isolated bipolar technology for analogue and digital applicationsxe2x80x9d, Proc. of IEEE 1988, Custom and Integr. Circuits Conf., N.Y., May 16-19. Thereby, the capacitance between the bottom diffusion and the substrate can be considerably reduced at the same time as the dimensions of the individual transistor can be reduced, in particular its extension in lateral directions, i.e., in directions along the surface of the silicon plate, and a better isolation mutually between components is obtained.
In directions along the surface of the structure in all these designs a lot of area is consumed for producing both the collector plug and the base connection diffusion, respectively, and devices for isolating transistors from each other.
U.S. Pat. No. 5,003,365 discloses a bipolar transistor of NPN-type. The connection to the N-collector area 6 is obtained by the fact that a trench, which is isolated by means of oxide on its sidewalls, is filled with electrically conducting polysilicon of type N+. A hole exists in the oxide layer in a sidewall of a trench, from which a limited region has been diffused from the filling material in the trench. This region obtains an approximatively semi-cylindrical shape, having the flat surface extending along a diameter plane located at the sidewall of the trench. Producing this hole in the sidewall oxide requires a plurality of extra processing steps. The transistor takes, owing to the connection of the collector through a trench, a small area on the substrate surface. By the fact that furthermore all of the width of the trench is used for connecting, the isolating function thereof is reduced and can result in undesired capacitances to the substrate.
In U.S. Pat. No. 5,496,745 a bipolar transistor is disclosed having a bottom diffusion 22 located under the active collector layer 23, where the bottom diffusion is directly connected to a contact plug 35 outside trenches, which define the collector layer. The transistor takes a large area of the substrate surface.
In U.S. Pat. No. 5,187,554 which corresponds to the published European patent application 0 303 435 a bipolar NPN-transistor having a buried collector region is disclosed. In FIGS. 3-5 it is illustrated how the collector region is connected to the exterior electrical contact through a recess made at least partly in an isolating trench, the recess being made at the inner sidewall of the trench. This construction results in a reduced area of the transistor produced and reduced parasitic capacitances.
It is an object of the present invention to provide a trench isolated transistor having improved performance.
In particular it is an object of the present invention to provide a trench isolated transistor having good performance which takes a little area on a substrate.
It is a further object of the present invention to provide a trench isolated transistor which has a capacitance between substrate and collector which is as small as possible.
It is a further object of the present invention to provide a device and a method for connecting to an inner conducting layer in a trench isolated semi-conductor device, which can be easily produced and can be carried out in a simple way, respectively, using a minimum number of extra steps when manufacturing the semi-conductor device.
It is a further object of the present invention to provide a device and a method for the connecting an inner conducting layer in a trench isolated semi-conductor device, which gives a minimum influence on the electric characteristics of the device, in particular the isolation thereof from other devices manufactured on the same substrate.
It is a further object of the present invention to provide a transistor isolated by a trench, in which the trench and trenches can be produced in an efficient way.
A bipolar device is of the general kind as disclosed in U.S. Pat. No. 5,187,554 cited above. It has an electric connection, having a small resistance, to an inner layer such as a bottom diffusion in a transistor and the connection takes a small area at the surface of the substrate. Thereby, also the transistor will take a small area of the substrate, and thereby the length of the bottom diffusion laterally can also be reduced resulting in a reduced capacitance to the substrate.
A problem to be solved by the invention is how it will be possible to provide a connection having small requirements of space, which at the same time can be produced in a simple way, using as few additional processing steps as possible and also using processing steps which can be easily executed.
In order to obtain an electric connection to an interior region or an interior layer, which has a good electric conductance and is located inside a bipolar semi-conductor device which is isolated by trenches, in particular a bottom diffusion, which forms a subcollector or a base contact, a hole in a trench is used. The interior region or layer is generally located under all of the active region of the bipolar device. The hole is filled with electrically conducting material and extends from the surface of the device as far down, that the electrically conducting material therein comes in contact with the interior region or the layer having a high conductivity. As in the patent U.S. Pat. No. 5,187,554 cited above thereby a semi-conductor device is obtained, which takes a small space laterally on a substrate. By the fact that the lateral length of the bottom diffusion thereby can also be reduced, since the connection is made at a side surface of the bottom diffusion and no area thereof in the direction of the surface is required for connecting, also the capacitance of the bottom diffusion to the substrate is reduced. Producing the hole may require one extra processing step, but the filling of the hole can be made at the same time as some layer is applied, which is required for producing other details of the bipolar device, for example at the same time as material is deposited in an emitter opening or that metal material is deposited for exterior connections. The hole can also, if required, be filled in an extra processing step.
The hole is advantageously located at the sidewall of the trench at the border surface thereof to the surrounding material, and then also forms an opening in the oxide layer, which an isolating trench conventionally has at its sidewalls. This opening in the oxide layer has an edge at the upper free surface of the device. A sidewall of the hole then coincides with an imagined portion of the side surface of the trench, i.e., a former side surface, which existed before the hole was produced. Thereby, the electrically conducting material in the hole comes in electrical contact with that region in the device outside the trench, which is located at the hole. By using a selective etching process only attacking material in trench but not material in the region laterally adjacent to the trench, this results in a simple production process. The hole in the trench thus extends from the opening of the trench at the surface of the device perpendicularly to the surface thereof downwards at a side of the trench, and it is further located at a distance from an opposite side of a trench, so that at the opposite side a region remains comprising the electrically isolating of semi-isolating material. Owing to this region which is considerably thicker than a thermal surface oxide, the capacitance of the material of the contact hole to the substrate material will be low.
The recess for contacting the interior such as a bottom diffusion is, e.g., for a lateral PNP-transistor made as a closed groove and thus has a ring shape. It extends around an active area of the device and confines by a first sidewall the active area of the device and thus has a direct border to the active area.
The electrically conducting material in the recess can include some type of highly doped silicon, such as doped amorphous silicon and/or doped microcrystalline silicon and/or doped polysilicon or even metal, in particular tungsten. The recess can, in one embodiment, be defined and etched at the same time as other contact holes to active areas of the device, and furthermore the recess can be filled at the same time as other contact holes by depositing tungsten using CVD-methods, so that no extra processing step is required for making the recess.
The trenches used in the device can be produced in the usual way by etching. Thereafter, on the walls of the trenches a laminated layer of at the bottom thermally grown silicon oxide and thereon a thin silicon nitride layer are applied by means of deposition. Finally the remaining main portions of the trenches are filled by applying a silicon oxide layer over the surface of the plate, for example by depositing of a suitable kind. The silicon nitride layer then acts as an etch stopping layer in a following planarizing etching step for planarizing that silicon oxide layer, with which the main portion of the trenches is filled. Furthermore, if the silicon oxide material used in the filling process would have impurities, the silicon nitride layer prevents that they diffuse into the substrate material. Such a diffusion could reduce the electrically isolating effect of the trenches.
The sidewalls of the annular groove can, as seen from above, be substantially parallel to each other and be located at a uniform distance from each other around all of the active area. The sidewalls extend advantageously along the outlines of two concentric rectangles or squares placed inside each other. Rectangular corners in the outline of the outer sidewall can be bevelled by 45xc2x0, so that this sidewall will always extend along a polygon, the inner angles of which all are equal to 135xc2x0, in order to facilitate, when producing the device, the refilling of the groove with the electrically conducting material. The same can advantageously also be true for the sidewalls of the trench. Generally, the corners of the exterior sidewall of the groove and also of the trench should have angles substantially exceeding 90xe2x80x2, in particular angles of substantially 135xc2x0 or at least 135xc2x0 in order to facilitate, when producing the device, the refilling of the groove or of the trench respectively with material.
When the device is a lateral PNP-transistor the emitter area and/or collector area of the transistor can, as to its extension laterally along the surface of the device, be determined by a lithographically defined opening in an electrically isolating surface layer. In the common way the emitter and collector areas can be surrounded, seen along the surface of the device, by thick field oxide regions, and then the electrically isolating surface layer extends up over and beyond the surrounding field oxide regions in a direction towards the active area, so that a strip of the electrically isolated surface layer is placed between the emitter or collector area, respectively, and the field oxide areas located most adjacent to this area. The electrically isolating surface layer comprises advantageously a laminate of silicon nitride and silicon oxide.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the methods, processes, instrumentalities and combinations particularly pointed out in the appended claims.